Some user-programmable integrated circuits, such as field programmable gate array (FPGA) integrated circuits, use static random access memory (RAM) memory to store the configuration data to control routing switches or multiplexers that are used to implement user circuits. FIGS. 1A through 1E show various static RAM switch configurations (see Brown, Francis, Rose, Vranesic, Field Programmable Gate Arrays, 1992). The RAM cell should consume a minimum amount of static power and occupy the smallest possible die area. A simple configuration is shown in FIG. 1A where the output of a single RAM memory cell controls an n-channel pass transistor switch to connect two routing wire segments to each other.
Modern FPGAs generally avoid the need for decoding logic by providing a separate RAM cell for each input of a multiplexer. Thus an N-input multiplexer implemented with a single level of N pass transistor switches would require N RAM cells. Each switch in the multiplexer is controlled by its own RAM cell in a manner similar to the circuit shown in FIG. 1A. It is also common for one RAM cell to be connected to the gates of several pass transistors to control several switches by simultaneously turning them all on or all off.
Some implementations employ CMOS transmission gates instead of single pass transistor switches, as shown in FIG. 1B, where the output of a single RAM memory cell controls an n-channel pass transistor switch connected in parallel with a p-channel pass transistor switch to connect two routing wire segments to each other. The output of the RAM cell is inverted to control the gate of the p-channel pass transistor switch.
FIG. 1C shows two bi-stable RAM cells connected to the control inputs of a 4-input multiplexer to provide a one-of-four connection between four routing wires and a logic cell input (not shown). The circuit of FIG. 1C requires performing one-of-four decoding of the two RAM cell outputs (the decoding is assumed to be inside the box labeled multiplexer) to provide four mutually exclusive signals.
FIG. 1D shows four bi-stable RAM cells controlling a 4:1 multiplexer. Unlike the circuit of FIG. 1C, the circuit of FIG. 1D does not require performing one-of-four decoding of the RAM cell outputs to provide four mutually exclusive signals, at the expense of using twice the number of RAM cells to provide the four mutually exclusive signals. Only one of the RAM cells is programmed to turn on its associated pass transistor to pass a selected one of the inputs to the output.
FIG. 1E shows eight bi-stable RAM cells controlling a 16:1 multiplexer. A first stage of the multiplexer uses four RAM cells to select one of four inputs from each of four first-stage multiplexers having four inputs. A second stage of the multiplexer uses four RAM cells to select the output of one of the four first-stage multiplexers. Like the circuit of FIG. 1D, the circuit of FIG. 1E does not require performing one-of-four decoding of the RAM cell outputs to provide four mutually exclusive signals. Only one of the RAM cells in each stage of the two-stage multiplexer is programmed to turn on its associated pass transistor to pass a selected one of the inputs to the output.
Previous designs use ordinary bistable or two-state SRAM cells, such as that shown in FIG. 2. Each memory cell includes n-channel transistor M1 connected in series with p-channel transistor M2 cross coupled to n-channel transistor M3 connected in series with p-channel transistor M4 as is known in the art.
Each column of RAM memory cells share two complementary bit lines (BL and BL_bar) that are connected to the memory cell by address transistors M5 and M6 and each row of cells share a word line (WL) that controls the gates of the address transistors. The Q output and optionally the Q_bar output may be used to drive the gates of one or more switches. A buffer or inverter may be placed between the Q or Q_bar output and the switch gate(s) to avoid disturbing the state of the RAM cell as the switch source/drain transitions between high and low voltage and circuit capacitance introduces transients on the switch gate.
Data is written to the memory cell using the bit lines when the row of cells is selected using the word line. The cell may also be read through the bit lines, or additional devices may be added to read the state of the RAM cell in other ways. The address transistors M5 and M6 must be larger than the others so that they can overpower the current state of the cell when writing a new state. In FinFET technologies where the sizes of the transistors are quantized, the address transistors would be 2× the size of the other transistors. The sizes of routing multiplexers in FPGAs vary widely. A common size is 16 inputs, implemented as four 4-input multiplexers feeding a 2nd level 4-input multiplexer. Four RAM cells would be used to control the first-level multiplexers, with each RAM cell controlling one switch in each multiplexer. Four more RAM cells would be used to control the switches in the 2nd level multiplexer.
Implementing this architecture requires the use of a fairly large number of transistors. It would be advantageous to provide a multi-state configuration RAM cell that can be configured using a smaller number of transistor devices.